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cyons2101 ovationons? ii wireless gaming laser navigation system-on-chip cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-44047 rev. *h revised january 12, 2011 features programmable blocks ? highly integrated wireless mouse-on-a-chip with programmable psoc ? microcontroller unit (mcu) ? 32 kb flash memory ? 2 kb static ram (sram) ? internal 24-, 12-, or 6- mhz main oscillator (imo) ? internal 32-khz low speed oscillator (ilo) ? 16 bit data report enables simultaneous high speed and high resolution tracking tracking performance ? continuously variable resolution 400 to 3200 counts per inch (cpi), independent of speed ? high speed with high accuracy tracking ? speed up to 75 inches per second (in/s) ? acceleration up to 30g peripheral interface ? spi master interface to radio for wireless applications ? fast or standard mode i 2 c 28 general-purpose input /output (gpio) pins ? port 0 ? 8 bits ? port 1 ? 8 bits with high curr ent capability, regulated output voltage, and 5 v input tolerance ? port 2 ? 8 bits ? port 3 ? 4 bits power ? internal power system enables operation from battery or external 2.7 v to 3.6 v supply ? battery input voltage of 0.8 v to 3.6 v allows operation from single or dual series cells ? self adjusting power saving modes on-chip laser ? vertical cavity surface emi tting laser (vcsel) integrated within the sensor package ? no calibration or alignment needed ? electrostatic discharge (esd) immunity: 2000 v human body model (hbm) ? wavelength: 840 to 870 nm ? iec 60825-1 class 1 safety: built-in eye-safe fault tolerant laser drive circuitry snap-on lens ? molded optic: self-aligning snap-on molded lens ? 6 mm distance between the printed circuit board (pcb) and tracking surface description the cyons2101 is a member of cypress semiconductor?s second generation laser navigat ion system-on-chip (soc) family of products. powered by the high-speed and high-precision opticheck? technology, along with the world-leading psoc technology, this family integrates the sensor, boost power regulator, and mcu functions into one chip. bundled with the vcsel in one package, the combination forms the market?s first true mouse-on-a-chip solution. the cyons2101 is the version that is designed for high-performance wireless gami ng mouse applications. enabled by the cypress 0.13-micron mixed signal process technology, the device integrates the optich eck sensor with mcu into a single silicon chip that allows seamless communication between sensor and a wireless radio ic. the sensor provides the best translation of high-speed hand motion into cursor motion on the pc. this highly integrated solution is programmable. it provides mouse suppliers the ease-of-us e to design a single pcb system and customize their product. with the vcsel integrated in the same package, designers do not need to calibrate the laser power during the manufacturing process. this greatly increases production throughput and reduces manufacturing costs. the innovative technology of ovationons? ii provides high precision, high-speed motion tracking, and low-power consumption. designers can select from a family of integration options, ranging from low-power to high-performance, to target different types of wired and wireless design applications. the cyons2101 solutions have a small form factor. along with the lens, each package forms a complete and compact laser tracking system. this datas heet describes the detailed technology capabilities of the cyons2101. figure 1. cyons2101/cyonslens2000 (2-piece system) [+] feedback
cyons2101 document number: 001-44047 rev. *h page 2 of 34 contents ovationons ii family performance table...................... 3 ovationons ii family applications ................................ 3 ovationons ii family function al description .. ............. 3 pin description ................................................................. 5 microcontroller system............. ....................................... 7 features ...................................................................... 7 psoc functional overview.............................................. 8 the psoc core ........................................................... 8 the analog multiplexer system................................... 8 additional system resources . .................................... 8 getting started.................................................................. 8 application notes ........................................................ 8 development kits ........................................................ 8 training ....................................................................... 8 cypros consultants .................................................... 8 solutions library.......................................................... 8 technical support ....................................................... 8 development tools .......................................................... 9 psoc designer software subsyst ems............. ........... 9 designing with psoc designer ..................................... 10 select user modules ................................................. 10 configure user modules....... ..................................... 10 organize and connect ............... .............. ........... ...... 10 generate, verify, and debug... .................................. 10 power supply connections ........................................... 11 overview ................................................................... 11 understanding dvdd................................................ 11 avdd, vrega, and vregd .................................... 11 using battery power.................................................. 11 using external power................................................ 11 filtering and grounding........... .............. .............. ...... 11 wireless mouse application ex ample ............ .............. 12 electrical specifications ................................................ 13 absolute maximum ratings..... .................................. 13 operating conditions................................................. 13 power consumption .................................................. 14 power specifications ................................................. 15 dc general purpose i/o specifications .................... 16 dc analog mux bus specificat ions........................... 17 dc low-power comparator specifications ............... 17 dc por and lvd specifications .............................. 17 dc programming specifications ............................... 18 ac chip level specifications .................................... 19 ac gpio specifications ............................................ 19 ac external clock specifications .............................. 20 ac analog mux bus specifications ........................... 20 ac programming specifications ................................ 20 ac spi specifications ............................................... 21 ac comparator specifications .................................. 24 ac i2c specifications................................................ 24 pcb land pads and keepout z ones .............. .......... 25 orientation of axes.................................................... 26 pcb mounting height and thi ckness........................ 26 thermal impedances ................................................ 27 solder reflow peak temperat ure ............................. 27 laser safety considerations ...... ................................... 28 laser output power .................................................. 28 laser output power test procedure......................... 28 registration assistance............................................. 28 development tool selection ...... .............. .............. ....... 29 software .................................................................... 29 mouse design kits .................................................... 29 development kits ...................................................... 29 evaluation tools........................................................ 29 device programmers................ ................................. 30 third party tools ....................................................... 30 package diagrams.......................................................... 31 ordering information...................................................... 32 ordering code definition........ ................................... 32 document conventions ................................................. 33 acronyms used ......................................................... 33 units of measure ....................................................... 33 numeric naming........................................................ 33 document history page ................................................. 34 sales, solutions, and legal information ...................... 34 worldwide sales and design supp ort............. .......... 34 products .................................................................... 34 psoc solutions ......................................................... 34 [+] feedback
cyons2101 document number: 001-44047 rev. *h page 3 of 34 ovationons ii family performance table ovationons ii family applications wired and wireless laser mice ? gaming, graphic design, desktop, and mobile mice optical trackballs battery powered devices motion sensing applications ovationons ii family functional description the ovationons ii family is a two-piece laser navigation soc kit containing the integrated ic package and the molded lens. the 2-kv esd-rated ic package in tegrates the vcsel and laser sensor soc. depending on th e product selected, the soc includes an mcu, flash, sram, two internal oscillators, capsense system, battery boost r egulator, power regulator, and full-speed usb. the molded lens collimates the vcsel beam and images the light scattered from the tracking surface on to the sensor portion of the laser detector. the lens has features for registration to the package and easily snaps on to the pc board. at the heart of the system is the opt icheck laser navigation engine. it supports all functions required for tracking, including laser power control, resolution control, and self-adjusting power reduction, which reduces power consumption when motion stops. the laser output power is pre-calibrated to meet the eye safety requirements of iec 60825 class 1. the navigation engine is accessed and controlled by an integrated psoc-based mcu. the interface between the two blocks is through a system bus and a collection of navigation engine interrupts. full details are available in the ovationons ii laser navigation system-on-chip trm (technical reference manual) or in the psoc designer integrated development environment (ide) software. in addition to controlling the navigation engine, the psoc mcu also serves as the main application processor. based on cypress?s m8c architecture, the psoc supports a rich instruction set, multiple processor speeds, and flexible gpios. its imo requires no external crystal. on-chip flash and ram allow entire navigation systems to be implemented with the single soc. the ovationons ii family supports a wide range of powering options. internal regulators minimize the need for external circuitry. depending on the product selected, the device can be powered from a usb 5-v supply, from a single battery, from dual batteries, or from an external supply. the configuration and use of the power blocks are contro lled with the in tegrated psoc. wired sensors include integrated full-speed usb. as with the navigation engine and power system, the usb block is controlled by the integrated psoc. all sensors support a 4-wire spi in terface. a typical use of the spi interface is to provide access to a radio for wireless applica- tions. an i 2 c interface is also included with all devices. the cyons2110 device also supports capsense functions, allowing additional features and differentiation in end products. all features of the ovationons ii family are configured using cypress?s psoc designer? software, allowing fast application development and time to market. the ovationons ii family block diagram is shown on figure 2 on page 4. it shows a true soc so lution that en ables design cycle reductions along with savings on manufacturing, pcb area, and component inventory management. the packaged solution delivers a fully integrated syst em that demonstrates tracking performance with efficient power consumption. parameter cyons2000 cyons2001 cyons2100 cyons2101 cyons2110 unit variable resolution 400, 800, 1600 400, 800, 1600 400?3200 400?3200 400?3200 cpi maximum speed 30 30 75 75 75 in/s maximum acceleration 20 20 30 30 30 g integrated mcu yes yes yes yes yes capsense ? no no no no 26 inputs flash 16 16 323232kb sram 2 2 2 2 2 kb interfaces full-speed usb 4-wire spi up to 28 gpios 4-wire spi up to 28 gpios full-speed usb 4-wire spi up to 28 gpio 4-wire spi up to 28 gpios full-speed usb 4-wire spi up to 28 gpios battery supply voltage na 0.8 to 3.6 na 0.8 to 3.6 0.8 to 3.6 v usb supply voltage 4.25 to 5.25 na 4.25 to 5.25 na 4.25 to 5.25 v external supply voltage 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 v zero motion 1 1 1 1 1 count [+] feedback
cyons2101 document number: 001-44047 rev. *h page 4 of 34 figure 2. block diagram sram interrupt controller sleep and watchdog multiple clock sources 32 khz internal low speed oscillator (ilo) 6/12/24 mhz internal main oscillator (imo) psoc core cpu core (m8c) supervisory rom (srom) flash nonvolatile memory system resources system bus system bus port 2 port 1 port 0 global analog interconnect 1.8v analog regulator spi master/ slave por and lvd full speed usb system resets internal voltage references three 16-bit programmable timers psoc core regulator digital clocks capsense system optichecktm navigation system ovation ii power system vcsel laser control dsp resolution control boost regulator 3.3v regulator f power bus power control battery filter port 3 note: shaded blocks indicate optional functions - refer to ovationons tm ii family performance table for details i2c slave adc [+] feedback
cyons2101 document number: 001-44047 rev. *h page 5 of 34 pin description this section describes, lists, and illustrates the cyons2101 devi ce pins and pinout configurations. the cyons2101 is available in a 42-pin quad flat no-leads (qfn) package. table 1. cyons2101 pin description pin name digital analog description 1 xres i active high external reset with internal pull down 2 boost_gnd power power boost regulator ground 3 boost_ind power power boost regulator inductor 4 vbatt power power boost regulator input 5 dvdd power power digital supply voltage and regulated output (see power supply connections on page 11) 6 vregd power power digital vreg 7 avdd power power analog supply voltage 8 vrega power power analog vreg 9 p2[7] i/o i gpio port 2 pin 7 10 p1[5] iohr i spi miso, i2c_sda, gpio port 1 pin 5 11 p1[3] iohr i spi clk, gpio port 1 pin 3 12 p2[3] i/o i gpio port 2 pin 3 13 p2[5] i/o i gpio port 2 pin 5 14 p1[7] iohr i spi ss, i2c_scl, gpio port 1 pin 7 15 p1[1] iohr i spi mosi, issp clk [1] , i2c_scl, gpio port 1 pin 1 16 p3[3] iohr i hclk (ocd high speed clock output), gpio port 3 pin 3 17 p1[0] i/o i issp data [1] , i2c_sda, gpio port 1 pin 0 18 p3[5] i/o i cclk (ocd cpu clock output), gpio port 3 pin 5 19 p1[6] iohr i gpio port 1 pin 6 20 p1[2] iohr i gpio port 1 pin 2 21 p2[2] i/o i gpio port 2 pin 2 22 p3[7] i/o i ocdoe (ocd mode direction pin), gpio port 3 pin 7 23 p3[1] i/o i ocdo (ocd odd data output), gpio port 3 pin 1 24 ocde ocd ocd ocde (ocd even data output) 25 avss power power analog ground 26 p2[1] i/o i gpio port 2 pin 1 27 p2[0] i/o i gpio port 2 pin 0 28 p1[4] iohr i ext clk, gpio port 1 pin 4 29 p2[4] i/o i gpio port 2 pin 4 30 dvss power power digital ground 31 p2[6] i/o i gpio port 2 pin 6 32 p0[0] i/o i gpio port 0 pin 0 33 p0[2] i/o i gpio port 0 pin 2 34 p0[4] i/o i gpio port 0 pin 4 35 p0[6] i/o i gpio port 0 pin 6 36 p0[1] i/o i gpio port 0 pin 1 [+] feedback
cyons2101 document number: 001-44047 rev. *h page 6 of 34 figure 3. pin diagram 37 p0[3] i/o i gpio port 0 pin 3 38 p0[5] i/o i gpio port 0 pin 5 39 p0[7] i/o i gpio port 0 pin 7 40 dnu do not use 41 dnu do not use 42 vprog power power power for issp cp dvss power power center pad (cp) must be connected to digital ground legend: i=input; o=output; h=5 ma high output drive, r=regulated output, ocd=on-chip debug table 1. cyons2101 pin description (continued) pin name digital analog description note 1. these are the in-system serial programming (issp) pins. unlik e other gpio?s, they are not high-impedance at power on reset (p or). see the technical reference manual (trm) at www.cypress.com or in the psoc designer development software for more details. cyons2101 qfn (top view) 35 31 30 29 28 27 26 25 36 42 41 40 39 38 37 xres 13 14 15 16 17 18 19 20 21 22 23 24 10 11 12 1 2 3 4 5 6 7 8 9 boost_gnd boost_ind vbatt dvdd vregd avdd vrega ai, p2[7] ai, spi miso, p1[5] ai, spi clk, p1[3] ai, p2[3] ai, p2[5] ai, spi ss, p1[7] ai, spi mosi, issp clk, p1[1] ai, hclk, p3[3] ai, issp data, p1[0] ai, cclk, p3[5] ai, p1[6] ai, p1[2] ai, p2[2] ai, ocdoe, p3[7] ai, ocdo, p3[1] ocde avss ai, p2[1] ai, p2[0] ai, ext clk, p1[4] ai, p2[4] dvss ai, p2[6] ai, p0[6] ai, p0[1] ai, p0[3] ai, p0[5] ai, p0[7] dnu dnu 32 ai, p0[0] 33 ai, p0[2] 34 ai, p0[4] vprog [+] feedback
cyons2101 document number: 001-44047 rev. *h page 7 of 34 microcontroller system features powerful harvard-architecture processor ? m8c processor speed up to 24 mhz ? low power at high speed ? interrupt controller ? operating temperature range: +5c to +45c flexible on-chip memory ? 32 kb flash program storage 50,000 erase and write cycles ? 2 kb sram data storage ? partial flash updates ? flexible protection modes ? in-system serial programming (issp) complete development tools ? free development tool (psoc designer) ? full featured in-circuit em ulator (ice) and programmer ? full speed emulation ? complex breakpoint structure ? 128 k trace memory precision programmable clocking ? internal 5.0% 6/12/24 mhz main oscillator ? internal 32 khz low speed oscillator ? support for optional external 32-khz crystal programmable pin configurations ? 25-ma sink current on all gpios ? pull-up, high-z, open drain, or strong drive modes on all gpios ? up to 28 analog inputs on gpio ? configurable inputs on all gpios ? selectable, regulated digital i/o on port 1 ? 3.3-, 2.5-, or 1.8-v output ? 3.0 v, 20 ma total port 1 source current ? 5-ma source current mode on ports 0 and 1 ? hot swap capable versatile analog mux ? common internal analog bus ? simultaneous connection of i/o combinations ? high power supply rejection ratio (psrr) comparator ? low dropout voltage regulator for the analog array additional syst em resources ? spi master and spi slave ? clock speed up to 12 mhz ? three 16-bit timers ? watchdog and sleep timers ? internal voltage reference ? integrated supervisory circuit ? analog-to-digital converter (adc) ? i 2 c slave [+] feedback
cyons2101 document number: 001-44047 rev. *h page 8 of 34 psoc functional overview cypress's programmable syste m-on-chip (psoc) on-chip controllers combine dynamic, configurable analog and digital blocks and an 8-bit mcu on a si ngle chip, repl acing multiple discrete components while delivering advanced flexibility and functionality. a psoc device includes configurable analog and digital blocks, and programmable interconnect. this architecture enables the creation of customized peripheral configurations, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of conve- nient pinouts. the architecture for this device family, as illustrated on figure 2 on page 4, contains: the core, the navigation sensor, the power system, and the system resource s. a common, versatile bus enables connection between i/o and the analog system. gpio is also included. the gpio provides access to the mcu and analog mux. the psoc core the psoc core is a powerful engine that supports a rich instruction set. the psoc co re encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, an imo, and an ilo. the cpu core , called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a 4 mips, 8-bit harvard-architecture microprocessor. system resources provide additional capability, such as config- urable usb and spi master-slave communication interface, three 16-bit programmable time rs, and various system resets supported by the m8c. the analog multiplexer system the analog mux bus connects to every gpio pin. pins are connected to the bus individually or in any combination. analog signals may be routed to an internal adc. other multiplexer applications include: chip-wide mux that enables analog input from any i/o pin crosspoint connection between any i/o pin combinations additional system resources system resources, some previ ously listed, provide additional capability useful to complete systems. additional resources include low voltage detection and power on reset. brief state- ments describing the merits of each system resource follows. the spi master/slave module ? provides communication over three or four wires. ? runs at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). an i 2 c slave module low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced power-on reset (por) circuit eliminates the need for a syst em supervisor. an internal reference provides an absolute reference for capac- itive sensing. getting started for in depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics an d skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. [+] feedback
cyons2101 document number: 001-44047 rev. *h page 9 of 34 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application requirements. psoc designer software accelerates system design and time-to-market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment incl uding in-circuit emulation (ice) and standard software debug features. psoc designer includes: application editor gui for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source code editor (c and assembly) free c compiler with no size restrictions or time limits built in debugger integrated circuit emulation (ice) built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to 4 full-duplex uarts, spi master and slave, and wire- less psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view you choose a base device to work with and then select different onboard analog and digital components called user modules that use th e psoc blocks. examples of user modules are adcs, dacs, amplifie rs, and filters. you configure the user modules for your chosen application and connect them to each other and to the proper pins. then you generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy deve lopment of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration allows for changing configurations at run time. in essence, this allows you to usemore than 100% of psoc?s resources for a given application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two - the choice is yours. assemblers. the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs fo r the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environ ment that provides hardware in-circuit emulation (ice), allowi ng you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow a designer to read and program and read and write data memory, read and write i/o registers, read and write cpu registers, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. online help system the online help system displays online, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. th is system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low cost, high functionality in-circuit emulator (ice) is available for development support. this hardware has the capability to progra m single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulat ion pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. [+] feedback
cyons2101 document number: 001-44047 rev. *h page 10 of 34 designing with psoc designer the development process for the psoc? device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. the psoc development process is summarized in four steps: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-down menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and ro uting so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applic ations in either c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback
cyons2101 document number: 001-44047 rev. *h page 11 of 34 power supply connections figure 4. power connections overview the cyons2101 incorporates a po werful and flexible powering system. it can be powered from one of two sources: a battery (one cell or two cells in series) or an external 3.3-v supply. additionally, the cyons2101?s internal regulators can supply current to external devices. th is section describes the capabil- ities and usage of the power system. refer to figure 4 for a block diagram of the cyon s2101?s power system. understanding dvdd dvdd is a unique pin because it serves as either an input or an output. when the device is powered from a battery (using the boost regulator), dvdd acts as an output, providing a 3.3-v voltage that can be used to power avdd, vregd, vrega, and external parts. when the device is powered from an external 3.3-v supply, dvdd acts as an input only. avdd, vrega, and vregd as with dvdd, these signals power the internal circuitry of the device. unlike dvdd, these are always inputs. they should be connected as shown in figure 4 . using battery power for wireless applications, the device may be powered by the boost regulator. in this conf iguration, boost_gnd should be connected to dvss, boost_ind, and vbatt pins should be connected as shown in figure 4 . do not run the device without the appropriate bypass capacitors, or excessive voltage may be generated across the inductor. vbatt connects to an internal low-pass filter. the filter output can be routed through the global analog interconnect to the device?s adc, enabling the battery voltage to be monitored. for designs using two series batteries, an option is to drive vrega directly from the battery output. doing so reduces the conversion loss in the boost regulator. however, take care to ensure that the battery voltage does not fall below 1.71 v. using extern al power the cyons2101 can also be powered from an external source. in this case, boost_gnd sh ould be connected to dvss, vdd5v and boost_ind should be left unconnected, and the external 3.3-v source should connect to dvdd. vbatt can be connected to dvss or left unconnected. filtering and grounding for all designs, it is important to provide proper grounding and isolation between the analog and digital power supplies. the analog and digital grounds should be isolated, except for a single connection point that is placed as close as possible to the device. on the supply side, an l-c filter should be placed between avdd and dvdd, as shown in figure 4 . 1.8v analog circuitry 3v analog circuitry 1.8v digital circuitry 3v digital circuitry 25 avss 30 dvss 1.8v analog regulator 1.8v psoc core regulator 8 vrega vregd 6 7 avdd 5 dvdd boost regulator battery filter 4 vbatt 47 uh 3 boost_ind global analog interconnect 2 boost_gnd battery 0.8 - 3.6v 22 uf 22 uf 10 nh external 3.3v supply, 15 ma max digital gnd digital gnd digital gnd digital gnd analog gnd analog gnd analog gnd cyons2101 digital gnd 22 uf [+] feedback
cyons2101 document number: 001-44047 rev. *h page 12 of 34 wireless mouse application example figure 5 shows an implementation of a wireless mouse. figure 5. wireless mouse lf_sw rt_sw ctr_sw fwd_sw bwd_sw z-wheel1 z-wheel2 z-wheel1 z-wheel2 lf_sw rt_sw ctr_sw fwd_sw bwd_sw rst mosi nss miso sck nss sck mosi miso radio_irq radio_irq dvcc dvcc avcc avcc vbat dvcc dvcc dvcc vcc filter optional switches e-pad must be soldered to ground. single point connection between analog and digital ground u2 cyrf6936 u2 cyrf6936 nc15 36 nc2 4 vbat2 8 resv 19 vcc3 16 nc9 20 nc1 2 sck 25 mosi 27 irq 26 xout 29 rst 34 miso 28 vcc1 3 vcc2 7 nc3 5 rfn 13 vbat1 6 l/d 37 xtal 1 ss 24 nc16 39 vreg 40 e-pad 41 vdd 35 nc4 9 nc5 14 rfbias 10 rfp 11 gnd1 12 nc6 15 nc7 17 nc8 18 nc10 21 pactl 30 nc11 22 vio 33 nc12 23 nc13 31 nc14 32 vbat0 38 sw1 sw pushbutton sw1 sw pushbutton sw5 sw pushbutton sw5 sw pushbutton u1 cyons2101 u1 cyons2101 boost_gnd 2 dvdd 5 dvss 30 boost_in 3 p2_7 9 avdd 7 hclk, p3_3 16 issp data, p1_0 17 vrega 8 ext clk, p1_4 28 p2_2 21 avss 25 spi miso, p1_5 10 spi mosi, issp clk, p1_1 15 spi ss, p1_7 14 spi clk, p1_3 11 p1_6 19 p1_2 20 ocdoe, p3_7 22 ocdo, p3_1 23 ocde 24 vbatt 4 p2_4 29 vregd 6 p2_1 26 p2_3 12 p2_5 13 cclk, p3_5 18 p2_0 27 p2_6 31 p0_0 32 p0_2 33 p0_4 34 p0_6 35 p0_3 37 p0_5 38 p0_7 39 dnu 40 dnu 41 vprog 42 p0_1 36 xres 1 l1 10nh l1 10nh c17 0.47 ufd c17 0.47 ufd ant1 wiggle 63 ant1 wiggle 63 1 2 c7 .1uf c7 .1uf c4 2.0 pfd c4 2.0 pfd c13 0.047 ufd c13 0.047 ufd sw4 sw pushbutton sw4 sw pushbutton c20 1.5 pfd c20 1.5 pfd r3 47 r3 47 c12 22uf c12 22uf c8 1 ufd c8 1 ufd c10 0.047 ufd c10 0.047 ufd sw3 sw pushbutton sw3 sw pushbutton d1 d1 2 1 c1 15 pfd c1 15 pfd l3 1.8 nh l3 1.8 nh l5 47 uh l5 47 uh c3 22uf c3 22uf c2 22uf c2 22uf r2 1 1% r2 1 1% l2 22 nh l2 22 nh en1 encoder en1 encoder com 1 gnd1 4 gnd2 5 qa 2 qb 3 c5 .1uf c5 .1uf sw2 sw pushbutton sw2 sw pushbutton c15 0.047 ufd c15 0.047 ufd c16 0.047 ufd c16 0.047 ufd c6 .1uf c6 .1uf c9 10 ufd c9 10 ufd c14 0.047 ufd c14 0.047 ufd c11 0.047 ufd c11 0.047 ufd y1 12 mhz crystal y1 12 mhz crystal c19 0.47 ufd c19 0.47 ufd [+] feedback
cyons2101 document number: 001-44047 rev. *h page 13 of 34 electrical specifications this section presents the dc and ac electric al specifications of the cyons2101 device . for the most up-to-date electrical speci fi- cations, confirm that yo u have the most recent datasheet by visiting http://www.cypress.com . absolute maximum ratings operating conditions parameter min typ max unit conditions storage temperature [2] ?40 25 65 c case temperature operating temperature ?15 ? 55 c case temperature lead solder temperature ? ? 260 c 10 seconds supply voltage, dvdd, avdd, vrega, and vregd relative to dvss) ??3.6 v supply voltage, vbatt relative to dvss ? ? 3.6 v esd ? ? 2.0 kv all pins, hbm mil 883 method 3015 i/o voltage relative to dvss ?0.5 ? dvdd + 0.5 v gpio ports 0, 2, and 3 i/o voltage relative to dvss ? ? 5.5 v gpio port 1 latch-up current ? ? 100 ma maximum current into any gpio pin ?25 ? +50 ma parameter min typ max unit conditions operating temperature 5 ? 45 c power supply voltage dvdd, avdd, vregd vrega vbatt 2.70 1.71 0.80 ? 3.60 3.60 3.60 v power supply rise time 100 ? ? s supply noise ? avdd (sinusoidal) ? ? 25 mv pp 10 khz to 50 mhz supply noise ? vdd, dvdd (sinusoidal) ? ? 100 mv pp 10 khz to 50 mhz distance from pcb to tracking surface 5.80 6 6.20 mm see figure 15 on page 26 pcb thickness 1.54 ? 1.79 mm see figure 15 on page 26 note 2. high storage temperature reduces flash data retention time specified in table 7 on page 18. recommended storage temperature is 25 25 c. extended duration above 65 c can degrade reliability. [+] feedback
cyons2101 document number: 001-44047 rev. *h page 14 of 34 power consumption introduction as described overview on page 11, the cyons2101 has a highly advanced power system, which can be used to develop very low power applications. this section describes and specifies the power consumption performance of the device. enabling low-power modes in some cases, designers ma y wish to develop ?always-on? applications, with no power saving modes and consequently no wakeup latency in performanc e. in other applications, conserving power is crucial and power-saving modes are a firm requirement. the cyons2101 allows low power modes to be enabled or disabled in firmware, ei ther through register writes or through the application programming interface in cypress?s psoc designer development software. the remainder of this section applies to applications requiring power saving modes. operating modes from a power consumption standpoint, consider these three operating modes. tracking mode: in this mode, the device is actively tracking on a surface. it is the highest power mode of the device. the current consumption has a slight dependence on speed and surface. the current, however, is independent of resolution. inactive mode: in this mode, the device is in its lowest power state. in inactive mode, the de vice cannot sense motion, but a timer is running. the timer can generate an interrupt that can wake the rest of the device and start tracking motion. sleep mode: in sleep mode, the device self-transitions between tracking mode and inactive mode. the typical use of sleep modes is when the device is at rest, but might still be moved. in sleep mode, the cyons2101 stays in inactive mode for a fixed time, then wakes up and checks for motion. if motion is detected, the device fully wakes up and begins tracking. if no motion is detected, the device can go back to sleep mode. power management through sleep mode control power management for the cyons2 101 consists of setting the parameters that define the sleep modes. the device is equipped with four sets of sleep mode se ttings, allowing four levels of sleep. by controlling the paramete rs of these four sleep modes, the designer can tailor the solution to make appropriate tradeoffs between power consumption and wakeup latency. the transition between sleep modes is under the control of the cyons2101?s digital signal processor (dsp) ? no firmware needs to be written to manage the transition between modes. each of the four available sl eep modes is defined by three parameters. these parameters are defined as registers that can be controlled by firmware, either through direct register writes or by using the nav user module in psoc designer. sleep time: this is the amount of time that the device is in its low power inactive state. motion threshold: this is the am ount of motion that is required to bring the device out of sleep. sleep mode time: this is the amount of time that the device stays in a particular sleep mode before transitioning to the next lowest sleep mode. longer sleep times saves power but have higher wakeup latency. figure 6 shows the flowchart for a particular sleep mode, showing how the three parameters affect behavior. calculating power for sleep mode the power consumption in sleep mode can be found by using a duty cycle calculation. the sleep mode current is determined by the tracking mode current, the inac tive current, the time required to check for motion (typically 2.9 ms), and the time between check-for-motion events. the expected current consumption is given by the formula where i sleep is the sleep current, i track is the tracking current, i inact is the inactive current, and t sleep is the time (in ms) in the low-power state. as an example, if the tracking current is 8.5 ma, the inactive current is 7.5 a and the sleep time is 100 ms, then the expected sleep current is 0.25 ma. figure 6. sleep mode flowchart i sleep i track 2.9 i inact t sleep + 2.9 t sleep + ---------------------------------------------------------------------------------- - = go to sleep for n ms wake up, check for motion motion > threshold t? time in mode > m sec? enter from higher sleep mode y y n n go to active tracking mode go to deeper sleep mode [+] feedback
cyons2101 document number: 001-44047 rev. *h page 15 of 34 power specifications there are two ways to powe r the cyons2101 ? external powering and battery powering. table 4 provides the current consumption values for each mode. with external powering, a 3-v supply is connected to dvdd, avdd, vregd, and vrega, and t he internal regulator is turned off. in this case, the current consumption during tracking is i track_ext , and the consumption during sleep is i sleep . with battery powering, the device is powered by the internal boost regulator. total tracking current must include the current consumed by the regulator itself, and is given by the sum of i track and i regboost . similarly, sleep current is given by the sum of i sleep and i regboost . in both cases, the current drawn from the battery must be adjusted by the voltage conversion ratio and the boost regulator efficiency track and inact . sleep current is achieved by activating ?navigation sleep modes? in cypress?s psoc designer development environment. doing so enables the sleep mode progressions described earlier. if sleep modes are not ac tivated, the device current stays at tracking levels, even when the device is not sensing motion. i sb is the current in the lowest-pow er mode of the device. in this mode, the cpu is halted and operation can only be restarted with an external reset at the xres pin. table 2. power specifications symbol description conditions min typ max units i track tracking current into dvdd, avdd, vregd, vrega 3.0 v, 25 c, 5 inch/second, 24 mhz imo, 6 mhz cpu clock, white surface, nominal tracking height ? 9 12.5 ma i inact inactive current into dvdd, avdd, vregd, vrega 3.0 v, 25 c, cpu in sleep state ? 7 14 a i sleep sleep current into dvdd, avdd, vregd, vrega 3.0 v, 25 c see calculating power for sleep mode on page 14 for equation i regboost boost regulator current consumption 3.0 v at vbatt, 25 c?20?a track boost converter efficiency, tracking mode 1.2 v vbatt input, 47 h inductor, 10 ma load, 400 khz switching frequency ?90? % inact boost converter efficiency, inactive mode 1.2 v vbatt input, 47 h inductor ? 70 ? % v boost_set boost converter nominal output programmed using psoc designer user module calibration feature 2.7?3.3v v boost [3] boost converter accuracy offset from set point ?10 ? +10 % i sb shutdown current into dvdd, avdd, vregd, vrega, all blocks off 3.0 v, 25 c?411a note 3. boost output specification requires us e of calibrated user module in psoc designer version 5.0 service pack 6 or later. [+] feedback
cyons2101 document number: 001-44047 rev. *h page 16 of 34 dc general purpose i/o specifications gpios are arranged into four ports. ports 0, 1, and 2 have eight gpio pins and port 3 has four gpio pins. port 1 has an optiona l low drop out (ldo) regulator that adjusts the port?s output volta ge to 1.8, 2.5, or 3.0 v. additionally, each gpio pin can be indep endently set to one of four drive modes: strong drive, open drain, pull-up, or hi-z analog. rise and fall times are specified for 10% and 90% voltage values. the following tables list guaranteed maximum and minimum specificatio ns for the voltage range of 2.7 v to 3.6 v at the dvdd pin , and over the temperature range 5 c t a 45 c. typical parameters apply to 3.3 v at 25 c and are for design guidance only. table 3. 2.7 v to 3.6 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor pin configured for pull-up mode. 4.0 5.6 8.0 k v oh1 high output voltage port 2 or 3 pins i oh < 10 a, maximum of 10 ma source current in all i/os. dvdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins i oh = 1 ma, maximum of 20 ma source current in all i/os. dvdd - 0.9 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 a, maximum of 10 ma source current in all i/os. dvdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 5 ma, maximum of 20 ma source current in all i/os. dvdd - 0.9 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh < 10 a, dvdd > 3.1 v, maximum of 4 i/os all sourcing 5 ma. 2.85 3.00 3.30 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh = 5 ma, dvdd > 3.1 v, maximum of 20 ma source current in all i/os. 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh < 10 a, dvdd > 2.7 v, maximum of 20 ma source current in all i/os. 2.35 2.50 2.75 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh = 2 ma, dvdd > 2.7 v, maximum of 20 ma source current in all i/os. 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 a, dvdd > 2.7 v, maximum of 20 ma source current in all i/os. 1.60 1.80 2.10 v v oh10 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, dvdd > 2.7 v, maximum of 20 ma source current in all i/os. 1.20 ? ? v v ol low output voltage i ol = 25 ma, dvdd > 3.3 v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]). ??0.75v v il input low voltage ? ? 0.80 v v ih input high voltage 2.00 ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) gross tested to 1 a. ? 0.5 1.0 a c pin pin capacitance te m p = 2 5 c. 0.5 1.7 8.0 pf [+] feedback
cyons2101 document number: 001-44047 rev. *h page 17 of 34 dc analog mux bus specifications the analog mux bus can connect signals from gpios to and from internal analog blocks and other gpios. ta b l e 4 lists guaranteed maximum and minimum specifications for th e entire voltage and temperature ranges. dc low-power comparator specifications the device includes two general-purpose comparators, using internal or external signals from the analog mux bus. table 5 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. dc por and lvd specifications the device features two mechanisms for dealing with low power s upply voltages. both power-on reset (por) and low voltage detect (lvd) events occur when dvdd falls below a threshold. a por comple tely resets the device. an lvd generates an interrupt to the mcu, allowing the application developer to better manage power supply drops. the por threshold is defined by bits 7 (hpor) and 5:4 (porlev) and of the vlt_cr register at address e3h in register bank 1. the lvd threshold is defined by bits 2:0 (vm) of the same register. refer to the technical reference manual for more details. ta b l e 6 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 4. dc analog mux bus specifications parameter description conditions min typ max unit r sw switch resistance to common analog bus pin voltage < 1.8 v ? ? 800 r gnd resistance of initializa tion switch to dvss pin voltage < 1.8 v ? ? 800 table 5. dc comparator specifications parameter description conditions min typ max unit v lpc low power comparator (lpc) common mode maximum voltage limited to dvdd. 0.0 ? 1.8 v i lpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv table 6. dc por and lvd specifications parameter description conditions min typ max unit v por0 v por1 v por2 v por3 dvdd value for por trip porlev[1:0] = 00b, hpor = 0 porlev[1:0] = 00b, hpor = 1 porlev[1:0] = 01b, hpor = 1 porlev[1:0] = 10b, hpor = 1 dvdd must be greater than or equal to 1.71 v during startup, reset from the xres pin, or reset from watchdog. 1.61 ? 1.66 2.36 2.60 2.82 1.71 2.40 2.65 2.95 v v v v v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 dvdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b 2.40 [4] 2.64 [5] 2.85 [6] 2.95 3.06 1.84 1.75 [7] 2.45 2.71 2.92 3.02 3.13 1.90 1.80 2.51 2.78 2.99 3.09 3.20 1.96 1.84 v v v v v v v notes 4. always greater than 50 mv above v por1 voltage for falling supply. 5. always greater than 50 mv above v por2 voltage for falling supply. 6. always greater than 50 mv above v por3 voltage for falling supply. 7. always greater than 50 mv above v por0 voltage for falling supply. [+] feedback
cyons2101 document number: 001-44047 rev. *h page 18 of 34 dc programming specifications ta b l e 7 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. the cyons2101 must be properly powered for flash programmi ng, with dvdd, avdd, vregd, and vrega all held within the specified range. a suitable option for power is to apply +5 v to vprog, and to connect dvdd, avdd, vregd and vrega together. in this option, there is no need to provide external powe r to the dvdd/avdd/vregd/vrega no de. if vprog is not used, the designer must include provisions for supply ing dvdd, avdd, vregd, and vrega externally. table 7. dc programming specifications parameter description conditions min typ max unit v 5vprog programming power for vprog 4.75 5.0 5.25 v i 5vprog vprog current for programming ? ? 25 ma v iw supply voltage for flash write operations v iw applied to dvdd, avdd, vregd, and vrega 2.7 ? 3.6 v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify see dc general purpose i/o specifications on page 16. ? ? v il v v ihp input high voltage during programming or verify see dc general purpose i/o specifications on page 16. v ih ? ? v i ilp input current when applying v ilp to issp clk and issp data pins during programming or verify driving internal pull-down resistor. ? ? 0.2 ma i ihp input current when applying v ihp to issp clk and issp data pins during programming or verify driving internal pull-down resistor. ? ? 1.5 ma v olp output low voltage during programming or verify ? ? dvss + 0.75 v v ohp output high voltage during programming or verify dc general purpose i/o specifications on page 16. for dvdd> 3 v use the value with i oh = 5 ma. v oh ? dvdd v flash enpb flash write endurance erase/write cycles by block. 50,000 ? ? cycles flash dr flash data retention following maximum flash write cycles at ambient temp of 45 c. 5 10 ? years [+] feedback
cyons2101 document number: 001-44047 rev. *h page 19 of 34 ac chip level specifications the device has two internal oscillators. the imo controls the cl ock speeds for the cpu. a programmable frequency divider allows the cpu to run at lower speeds than the imo. the ilo is a typically active in sleep modes, clocking sleep, and watchdog timers. oth er internal timers can be clocked by either the cpu clock or the ilo. ta b l e 8 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. ac gpio specifications gpios are arranged into ports. ports 0, 1, and 2 have eight gpio pins and port 3 has four gpio pins. port 1 has an optional ldo regulator that adjusts the port?s output vo ltage to 1.8, 2.5, or 3.0 volts. additionally, each gpio pin can be independently se t to one of four drive modes: strong drive, o pen drain, pull-up, or high-z analog. rise and fall times are specified for 10% and 90% voltage values. specifications are for the entire operating temperature range. table 8. ac specifications parameter description min typ max unit f imo24 imo frequency for 24 mhz setting 22.8 24 25.2 mhz f imo12 imo frequency for 12 mhz setting 11.4 12 12.6 mhz f imo6 imo frequency for 6 mhz setting 5.7 6.0 6.3 mhz dc imo imo output duty cycle at 6 and 12 mhz setting [8] 40 50 60 % f cpu cpu frequency [9] f imo / 256 ? f imo mhz f 32k1 ilo frequency [10] 19 32 50 khz t ramp supply ramp time 20 ? ? s txrst external reset pulse width at power-up 1 ? ? ms txrst2 external reset pulse width after power-up 10 ? ? s tmot motion delay from reset to valid tracking data [11] ? ? 30 ms table 9. ac gpio specs parameter description conditions min typ max units f gpio gpio operating frequency strong drive 0 ? 12 mhz t rise_01 rise time, ports 0 -1 strong drive, c load = 50 pf, dvdd = 3.0 - 3.6 ? ? 50 ns t rise_01_l rise time, ports 0 -1, low supply strong drive, c load = 50 pf, dvdd = 2.7 - 3.0 ? ? 70 ns t rise_ldo_3 rise time, port 1, 3 v ldo enabled strong drive, c load = 50 pf, dvdd > 3.1 v ? ? 50 ns t rise_ldo_2.5 rise time, port 1, 2.5 ldo enabled strong drive, c load = 50 pf, dvdd > 2.7 v ? ? 70 ns t rise_ldo_1.8 rise time, port 1, 1.8 ldo enabled strong drive, c load = 50 pf, dvdd > 2.7 v ? ? 100 ns t rise_23 rise time, ports 2 - 3 strong drive, c load = 50 pf, dvdd = 2.7 - 3.6 ? ? 80 ns t fall fall time, all ports strong drive, c load = 50 pf, dvdd = 3.0 - 3.6 ? ? 50 ns t fall_l fall time, all ports, low supply strong drive, c load = 50 pf, dvdd = 2.7 - 3.0 ? ? 70 ns t fall_ldo_3 fall time, port 1, 3 v ldo enabled strong drive, c load = 50 pf, dvdd > 3.1 v ? ? 50 ns t fall_ldo_2.5 fall time, port 1, 2.5 ldo enabled strong drive, c load = 50 pf, dvdd > 2.7 v ? ? 70 ns t fall_ldo_1.8 fall time, port 1, 1.8 ldo enabled strong drive, c load = 50 pf, dvdd > 2.7 v ? ? 80 ns notes 8. imo can be output from chip by routing to gpio. maximum gpio output frequency is 12 mhz, so duty cycle at 24 mhz is not defin ed. see technical reference manual at www.cypress.com or in cypress's psoc designer software for details on routing imo to gpio pin. 9. available frequency divisors are 1, 2, 4, 8, 16, 32, 128, and 256. 10. 32 khz oscillator can be locked to external crystal. see techni cal reference manual available at www.cypress.com or in cypre ss?s psoc designer software. 11. value provided represents maximum startup time for typical appl ication. applications requiring additional startup code, proc essing, or delay may increase tmot. [+] feedback
cyons2101 document number: 001-44047 rev. *h page 20 of 34 ac external clock specifications the imo can be replaced with an external clo ck at the ext clk / p[1]4 pin. refer to the technical reference manual for more details. ta b l e 1 0 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. ac analog mux bus specifications the analog mux bus can connect sig nals from gpios to and from intern al analog blocks a nd other gpios. ta b l e 11 lists guaranteed maximum and minimum specifications for th e entire voltage and temperature ranges. ac programming specifications ta b l e 1 2 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 10. ac external clock specifications parameter description min typ max unit f oscext frequency 0.750 ? 25.2 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? required time to run from imo befor e switching to external clock 150 ? ? s table 11. ac analog mux bus specifications parameter description conditions min typ max unit f sw switch rate pin voltage < 1.8 v ? ? 6.3 mhz table 12. ac programming specifications symbol description conditions min typ max units t rsclk rise time of issp clk 1 ? 20 ns t fsclk fall time of issp clk 1 ? 20 ns t ssclk data setup time to falling edge of issp clk 40 ? ? ns t hsclk data hold time from falling edge of issp clk 40 ? ? ns f sclk frequency of issp clk 0 ? 8 mhz t eraseb flash erase time (block) ? ? 18 ms t write flash block write time ? ? 25 ms t dsclk2 data out delay from falling edge of issp clk 3.0 dvdd 3.6 ? ? 85 ns [+] feedback
cyons2101 document number: 001-44047 rev. *h page 21 of 34 ac spi specifications ta b l e 1 3 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 14. ac spi slave specifications table 13. ac spi master specifications parameter description min typ max unit f sclk spi clk frequency [12] ? ? f imo /2 mhz t setup spi miso to spi clk setup time 60 ? ? ns t hold spi clk to spi miso hold time 40 ? ? ns t out_su spi mosi to spi clk setup time 40 ? ? ns t out_h spi clk to spi mosi hold time 40 ? ? ns notes 12. clock frequency is half of clock input to spi block. 13. value corresponds to 50% duty cycle at 12 mhz. parameter description min typ max unit f sclk spi clk frequency [12] ? 12 mhz t low minimum spi clk low width [13] 41.67 ? ? ns t high minimum spi clk high width [13] 41.67 ? ? ns t setup spi mosi to spi clk setup time 25 ? ? ns t hold spi clk to spi mosi hold time 25 ? ? ns t out_h spi clk to spi miso hold time 35 ? ? ns t ss_miso spi ss to spi miso valid ? ? 100 ns t sclk_miso spi clk to spi miso valid ? ? 140 ns t ss_high minimum spi ss high width ? ? 35 ns t ss_clk time from spi ss low to first spi clk ? ? 20 ns t clk_ss time from last spi clk to spi ss high ? ? 25 ns [+] feedback
cyons2101 document number: 001-44047 rev. *h page 22 of 34 figure 7. spi master timing diagram, modes 0 and 2 figure 8. spi master timing diagram, modes 1 and 3 [+] feedback
cyons2101 document number: 001-44047 rev. *h page 23 of 34 figure 9. spi slave timing diagram, modes 0 and 2 figure 10. spi slave timi ng diagram, modes 1 and 3 [+] feedback
cyons2101 document number: 001-44047 rev. *h page 24 of 34 ac comparator specifications the device includes two general-purpose comparators, using internal or external signals from the analog mux bus. ta b l e 1 5 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. ac i 2 c specifications ta b l e 1 6 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. figure 11. timing for fast/standard mode on the i 2 c bus table 15. ac low power comparator specifications symbol description conditions min typ max units t lpc comparator response time, 50 mv overdrive 50 mv overdrive does not include offset voltage. ? ? 100 ns table 16. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scli2c i2c_scl clock frequency 0 100 0 400 khz t hdstai2c hold time for start and repeated start condition 4.0 ?0.6 ? s t lowi2c low period of the i2c_scl clock 4.7 ?1.3 ? s t highi2c high period of i2c_scl clock 4.0 ?0.6 ? s t sustai2c setup time for a start and repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ? 100 [14] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes that ar e suppressed by the input filter ? ? 0 50 ns i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition note 14. a fast-mode i 2 c-bus device can be used in a standard mode i 2 c-bus system, but the requirement t sudati2c 250 ns must then be met. this automatically is the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. [+] feedback
cyons2101 document number: 001-44047 rev. *h page 25 of 34 pcb land pads and keepout zones figure 12 and figure 13 show the recommended land pad architecture and k eepout zones. the pads on the 42-pin device are a subset of the jedec mo-220 52-pin qfn standard. for de tailed layout instructions, see application note an48995, mechanical design considerations for the ovationons tm ii laser navigation system-on-chip . figure 12. land pad architecture and spacing figure 13. pcb keep out zones [+] feedback
cyons2101 document number: 001-44047 rev. *h page 26 of 34 orientation of axes figure 14 describes the relationship between the package and the x/y axes when using the api provided by cypress?s psoc designer software. note that there is a 90-degree rotation between the orientation below and the orientation described in the register s ection of the technical reference manual. if psoc designer is not used, the application fi rmware should read and invert the y count register for x data, and read the x count register for y data. figure 14. sensor orientation pcb mounting height and thickness figure 15 shows the recommended thickness and mounting he ight of the pcb above the tracking surface. figure 15. pcb height and thickness [+] feedback
cyons2101 document number: 001-44047 rev. *h page 27 of 34 thermal impedances solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 17. thermal impedances per package package typical ja [15] 42 pqfn [16] 24 c/w table 18. solder reflow peak temperature package minimum peak temperature [17] maximum peak temperature 42 pqfn 240c 260c notes 15. t j = t a + power x ja . 16. to achieve the thermal impedance specifi ed for the qfn package, the center thermal pad must be soldered to the pcb ground pl ane. 17. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5c with sn -pb or 245 5c with sn-ag-cu paste. refer to the solder manufacturer specifications.for a recommended soldering profile, refer to application note 49035, manufacturing considerations for the ovation- ons tm laser navigation system-on-chip . [+] feedback
cyons2101 document number: 001-44047 rev. *h page 28 of 34 laser safety considerations the cyons2101 laser navigation soc and the cyonslens2000 lens are designed and tested to enable manufacturers to achieve eye safety certification with minimal effort. this section provides guidelines for complying with the class 1 emission requirements of iec/en 60825-1. when installed and operated in accordance with all requirements in this data sheet, the kit consisting of the cyons2101 laser navigation soc and cyonslens2000 satisfies cdrh 21 cfr 1040 per laser notice #50 and iec/en 60825-1 class 1. laser output power the cyons2101 sensor package contains an integrated vcsel and drive circuitry. before shipping, cypress adjusts the laser output power to eye-safe levels, taking into account specified variations in supp ly voltage, temperature, lens transmission, and vcsel polarization, and factors such as vcsel aging and test equipment accuracy. the output remains within eye-safe limits under reasonably foreseeable single-faults, as required by the iec standard. from the perspective of a manufacturer, laser emission remains within the class 1 limit, as defined in iec 60825-1, edition 2, 2007, provided the following requirements are met. the supply voltage applied to pins dvdd and avdd of the soc must be in the range of 2.7 to 3.6 v. the operating temperature must be between 5 and 45 c. the laser output power must not be increased by any means, including but not limited to firmware, hardware, or mechanical modifications to the sensor or lens. the mechanical housing must be designed such that the cyonslens2000 cannot be removed by the user. the device firmware must initialize the vcsel driver as described in the ?vcsel driver? chapter of the ovationons ii technical reference manual or by using the nav or lasernav user modules in cypress?s psoc designer software. the manufacturer must ensure th ese conditions are always met and demonstrate end-product compliance to the appropriate regulatory standards. laser output power test procedure to verify the laser output level, follow the steps shown in the ?vcsel power calibration and verification? section of the technical reference manual . registration assistance the mouse or end-product supplier is responsible for certifying the end-use product with respect to the drive voltage, manuals and labels, and operating te mperature specifications. additionally, for products sold in the us, a cdrh report must be filed for each model produced, a nd test and inspection of the product?s characteristics as they relate to laser safety and the cdrh requirements must be performed. when filing a report with the cdrh, the supplier can refer to the product report filed by cypress for the cyons2xxx family of products. the cypress report is based on the previously-noted limits for voltage and temperature, and describes how the sensor design includes consideration of drive circuit failures, laser output variation with temperatur e, drive circuit variation with temperature and voltage, polar ization sensitivity of molded optics, and measurement uncertainties. cypress can provide assistance to customers who wish to obtain registration. supporting documentation, including a verification test procedure to demonstrate end-product compliance with iec and cdrh requirements is available. for further information, contact a cypress representative. [+] feedback
cyons2101 document number: 001-44047 rev. *h page 29 of 34 development tool selection this section presents the development tools available for all current psoc device families including the cyons2101. software psoc designer at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com/psocdesigner and includes a free c compiler with version service pack 4.5 or later. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice- cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress. com/psocprogrammer. mouse design kits two kits featuring the ovationo ns ii family of products are available. the reference design kit provides a complete hardware, firmware, and software solution, ready for production. the demonstration kit provides tested hardware and firmware that demonstrate the capabilities of the ovationons ii device. cy4631 wired mouse reference design kit wireless mouse demonstration kit development kits you can purchase the development kits from the cypress online store. cy3215-dk basic development kit the cy3215-dk kit enables prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. advanced emulation features ar e also supported through psoc designer. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable two cy8c29466-24pxi 28-pdip chip samples evaluation tools you can purchase the evaluation tools from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit enables a user to program psoc devices using the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiomete r, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a devel- opment board for the cy8c24794-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, poten tiometer, leds, an enunciator and plenty of bread boarding spac e to meet all of your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack [+] feedback
cyons2101 document number: 001-44047 rev. *h page 30 of 34 device programmers you can purchase the device programmers from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs spec ial software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable third party tools several tools have been specially designed by third-party vendors to accompany psoc devices during development and production. specific details for each of these tools are found at http://www.cypress.com . [+] feedback
cyons2101 document number: 001-44047 rev. *h page 31 of 34 package diagrams figure 16. qfn package detail - a detail - b top view bottom view seating plane side view scale: 2/1 scale: 2/1 ~ see detail - a see detail - b ~ pin 1 2 0.42-0.00 x 45 [4x] 0.20 max 1.40 max 0.05 max ?0.64 +0.025 -0.025 thru non-solderable pads 0.50-0.60 0.50-0.60 (pin1 id) [2x] 8.300 sq ?0.64 +0.025 -0.025 thru [2x] notes: 1. all dimensions are in mm , [ min/max] 2. refrence jedec # mo-220 3. pkg weight: 0.2 grams 4. aperture mold cavity i .d. +0.05 001-44934 *c [+] feedback
cyons2101 document number: 001-44047 rev. *h page 32 of 34 figure 17. lens ordering information the cyons2101 and cyonslens2000 are sold separate ly. when placing orders, order both part numbers. ordering code definition 001-44677 *b part number package application CYONS2101-LBXC 42 pin pqfn high performance wireless cyonslens2000-c lens - 4 mm height molded optic cy optical navigation sensor ons wired laser navigation system-on-chip company id : cy = cypress xxxx - xxx c 42- pin pqfn package temperature range: commercial [+] feedback
cyons2101 document number: 001-44047 rev. *h page 33 of 34 document conventions acronyms used ta b l e 1 9 lists the acronyms used in this document. units of measure the units of measure in ta b l e 2 0 lists the abbreviations used to measure the devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or ?0x? are decimal. table 19. acronyms acronym description acronym description ac alternating current ldo low drop out (regulator) adc analog to digital converter led light emitting diode api application programming interface lpc low power comparator cdrh center for devices and radiological health lsb least-significant bit cpi counts per inch lvd low voltage detect cpu central processing unit m8c cypress? 8-bit cpu core dac digital to analog converter mcu microcontroller unit dc direct current mips million instructions per second dsp digital signal processor msb most-significant bit esd electrostatic discharge mux multiplexer gnd ground pc, pcb printed circuit, printed circuit board gpio general purpose i/o pdip plastic dual in-line package hex hexadecimal pga programmable gain amplifier hi-z high impedance por power on reset i 2 c inter-integrated circuit (bus) pqfn plastic quad flat no-leads (package) ice in-circuit emulator psoc programmable system-on-chip idac dac-controlled current source psrr power supply rejection ratio ide integrated development environment pwm pulse width modulator iec international electrotechnical commission qfn quad flat no-leads (package) ilo internal low speed oscillator soc system on chip imo internal main oscillator spi serial peripheral interface (bus) i/o input/output sram static random access memory jedec joint electron devices engineering council usb universal serial bus lcd liquid crystal display vcsel vertical cavity surface emitting laser table 20. units of measure symbol unit of measure symbol unit of measure c degree celsius v microvolts g acceleration of gravity ma milliampere kb 1024 bytes ms millisecond in/s inches per second mv millivolt khz kilohertz nh nanohenry k kilohm nm nanometer kv kilovolt ns nanosecond mhz megahertz ohm a microampere pf picofarad f microfarad pp peak-to-peak h microhenry v volt s microsecond w watt [+] feedback
document number: 001-44047 rev. *h revised january 12, 2011 page 34 of 34 ovationons?, opticheck?, and psoc designer? are trademarks and psoc and capsense are registered trademarks of cypress semicondu ctor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. cyons2101 ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: cyons2101 ovationons? ii wire less gaming laser navigation system-on-chip document number: 001-44047 revision ecn orig. of change submission date description of change ** 2261927 fjz see ecn cyons2101 new data sheet. *a 2580125 fjz/pyrs 10/07/08 extensive updates *b 2769396 fjz/aesa 25/09/09 updated gett ing started and development tools sections. updated thermal impedance, wireless kit part number, flash specs, storage temperature, i2c footnote, external mode po wering, reference schemati c, power specifications, pin table, and c compiler information. *c 2889331 fjz 03/09/10 added table of contents. updated package diagram and sales links. *d 2903558 fjz 04/20/10 update lvd, usb, spi master and spi slave specs, nu merous minor updates for improved clarity and consistency *e 2936335 mmcy 05/24/2010 updated c ontent to match the new template and style guide. no technical updates. *f 3092209 fjz 11/22/2010 corrected error in pin description . removed invalid reference to application note in registration assistance . *g 3126503 fjz 01/03/2011 updated figure 17 . changed posting to external web *h 3135295 gnkk 01/12/2011 removed extr a blank page from the document. [+] feedback

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